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| AT90S8515 Features * * * * * * * * * * * * * * * * * * * * * Utilizes the AVR (R) Enhanced RISC Architecture AVR - High Performance and Low Power RISC Architecture 120 Powerful Instructions - Most Single Clock Cycle Execution 8K bytes of In-System Reprogrammable Downloadable Flash - SPI Serial Interface for Program Downloading - Endurance: 1,000 Write/Erase Cycles 512 bytes EEPROM - Endurance: 100,000 Write/Erase Cycles 512 bytes Internal SRAM 32 x 8 General Purpose Working Registers 32 Programmable I/O Lines Programmable Serial UART SPI Serial Interface VCC: 2.7 - 6.0V Fully Static Operation, 0 - 20 MHz Instruction Cycle Time: 50 ns @ 20 MHz One 8-Bit Timer/Counter with Separate Prescaler One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes Dual PWM External and Internal Interrupt Sources Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator Low Power Idle and Power Down Modes Programming Lock for Software Security 8-Bit Microcontroller with 8K bytes Downloadable Flash Preliminary AT90S8515 Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR (R) enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Pin Configurations 0841A 5-5 Block Diagram Figure 1. The AT90S8515 Block Diagram 5-6 AT90S8515 AT90S8515 Description (Continued) The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90S8515 provides the following features: 8K bytes of Downloadable Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/ counters, SPI port and interrupt system to continue functioning. The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The device is manufactured using Atmel's high density non-volatile memory technology. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT90S8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90S8515 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 5-7 Pin Descriptions VCC Supply voltage GND Ground Port A (PA7..PA0) Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pullups (selected for each bit). The Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current (IIL) if the internal pullups are activated. Port A serves as Multiplexed Address/Data input/output when using external SRAM. Port B (PB7..PB0) Port B is an 8-bit bidirectional I/O pins with internal pullups. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current (IIL) if the pullups are activated. Port B also serves the functions of various special features of the AT90S8515 as listed on Page 5-62. Port C (PC7..PC0) Port C is an 8-bit bidirectional I/O port with internal pullups. The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current (IIL) if the pullups are activated. Port C also serves as Address output when using external SRAM. Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pullups. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current (IIL) if the pullups are activated. Port D also serves the functions of various special features of the AT90S8515 as listed on Page 5-68. RESET Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier ICP ICP is the input pin for the Timer/Counter1 Input Capture function. OC1B OC1B is the output pin for the Timer/Counter1 Output CompareB function 5-8 AT90S8515 AT90S8515 ALE ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the loworder address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the second access cycle. Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. Figure 2. Oscillator Connections Figure 3. External Clock Drive Configuration 5-9 AT90S8515 AVR Enhanced RISC Microcontroller CPU The AT90S8515 AVR RISC microcontroller is upward compatible with the AVR Enhanced RISC Architecture. The programs written for the AT90S8515 MCU are fully compatible with the range of AVR 8-bit MCUs (AT90Sxxxx) with respect to source code and clock cycles for execution. Architectural Overview The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bits X-register, Y-register and Z-register. Figure 4. The AT90S8515 AVR Enhanced RISC Architecture The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S8515 AVR Enhanced RISC microcontroller architecture. 5-10 AT90S8515 AT90S8515 In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/Dconverters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is prefetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory. With the relative jump and call instructions, the whole 4K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space. The 512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. Figure 5. Memory Maps A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt address vector the higher priority. 5-11 The General Purpose Register File Figure 6 shows the structure of the 32 general purpose working registers in the CPU. 7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X-register low byte X-register high byte Y-register low byte Y-register high byte Z-register low byte Z-register high byte $0D $0E $0F $10 $11 0 Addr. $00 $01 $02 Figure 6. AVR CPU General Purpose Working Registers All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two registers or on a single register apply to the entire register file. As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X ,Y and Z registers can be set to index any register in the file. THE X-REGISTER, Y-REGISTER AND Z-REGISTER The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as: 15 X - register 7 R27 ($1B) 0 7 R26 ($1A) 0 0 15 Y - register 7 R29 ($1D) 0 7 R28 ($1C) 0 0 15 Z - register 7 R31 ($1F) 0 7 R30 ($1E) 0 0 Figure 7. The X, Y and Z Registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). 5-12 AT90S8515 AT90S8515 The ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logic and bit-functions. Some microcontrollers in the AVR product family feature a hardware multiplier in the arithmetic part of the ALU. The Downloadable Flash Program Memory The AT90S8515 contains 8K bytes on-chip downloadable Flash memory for program storage. Since all instructions are 16or 32-bit words, the Flash is organized as 4K x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. The AT90S8515 Program Counter (PC) is 12 bits wide, thus addressing the 4096 program memory addresses. See Page 5-78 for a detailed description on Flash data downloading. Constant tables must be allocated within the address 0-4K (see the LPM - Load Program Memory instruction description). See Page 5-14 for the different program memory addressing modes. The SRAM Data Memory - Internal and External The following figure shows how the AT90S8515 SRAM Memory is organized: Register File R0 R1 R2 ... R29 R30 R31 I/O Registers $00 $01 $02 ... $0020 $0021 $0022 ... Data Address Space $0000 $0001 $0002 ... $001D $001E $001F $3D $3E $3F $005D $005E $005F Internal SRAM $0060 $0061 ... $025E $025F External SRAM $0260 $0261 ... $FFFE $FFFF Figure 8. SRAM Organization The lower 608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 512 locations address the internal data SRAM. An optional external data SRAM can be placed in the same SRAM memory space. This SRAM will occupy the location following the internal SRAM and up to as much as 64K - 1, depending on SRAM size. 5-13 When the addresses accessing the data memory space exceeds the internal data SRAM locations, the external data SRAM is accessed using the same instructions as for the internal data SRAM access. When the internal data space is accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR register. See Page 5-31 for details. Accessing external SRAM takes one additional clock cycle per byte compared to the internal SRAM. This applies to commands LD, ST, LDS, STS, PUSH, POP. If the stack is placed in the external SRAM, interrupts, subroutine calls and returns will require two more clock cycles. When the external SRAM is used with wait state, all external SRAM access takes four clock cycles extra. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y and Z are decremented and incremented. The 32 general purpose working registers, 64 I/O registers, the 512 bytes of internal data SRAM, and the 64K bytes of optional external data SRAM in the AT90S8515 are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes. The Program and Data Addressing Modes The AT90S8515 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM, Register File and I/O Memory). This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. REGISTER DIRECT, SINGLE REGISTER RD Figure 9. Direct Single Register Addressing The operand is contained in register d (Rd). 5-14 AT90S8515 AT90S8515 REGISTER DIRECT, TWO REGISTERS RD AND RR Figure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O DIRECT Figure 11. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. DATA DIRECT Figure 12. Direct Data Addressing A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. 5-15 DATA INDIRECT WITH DISPLACEMENT Figure 13. Data Indirect with Displacement Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction word. DATA INDIRECT Figure 14. Data Indirect Addressing Operand address is the contents of the X, Y or the Z-register. DATA INDIRECT WITH PRE-DECREMENT Figure 15. Data Indirect Addressing With Pre-Decrement The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y or the Z-register. 5-16 AT90S8515 AT90S8515 DATA INDIRECT WITH POST-INCREMENT Figure 16. Data Indirect Addressing With Post-Increment The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z-register prior to incrementing. CONSTANT ADDRESSING USING THE LPM INSTRUCTION Figure 17. Code Memory Constant Addressing Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 4K) and LSB, select low byte if cleared (LSB = 0) or high byte if set (LSB = 1). DIRECT PROGRAM ADDRESS, JMP AND CALL Figure 18. Direct Program Memory Addressing Program execution continues at the address immediate in the instruction words. 5-17 INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL Figure 19. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Z-register). RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL Figure 20. Relative Program Memory Addressing Program execution continues at address PC + k. The relative address k is 2K. 5-18 AT90S8515 AT90S8515 The EEPROM Data Memory The AT90S8515 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on Page 5-44 specifying the EEPROM address registers, the EEPROM data register, and the EEPROM control register. For the SPI data downloading, see Page 5-78 for a detailed description. Memory Access Times and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock O, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. T1 T2 T3 T4 System Clock O 1'st Instruction Fetch 1'st Instruction Execute 2'nd Instruction Fetch 2'nd Instruction Execute 3'rd Instruction Fetch 3'rd Instruction Execute 4'th Instruction Fetch Figure 21. The Parallel Instruction Fetches and Instruction Executions 5-19 Figure 22 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. T1 T2 T3 T4 System Clock O Total Execution Time Register Operands Fetch ALU Operation Execute Store Result in Register Figure 22. Single Cycle ALU Operation The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. T1 T2 T3 T4 System Clock O Internal Address Bus Internal Read Signal Internal Data Bus (read) Internal Write Signal Internal Data Bus (write) Figure 23. On-Chip Data SRAM Access Cycles 5-20 AT90S8515 AT90S8515 The external data SRAM access is performed in two System Clock cycles as described in Figure 23 . T1 T2 T3 T4 S y s te m C lo c k O E x te rn a l A d d re ss [7 ..0 ] E x te rn a l A d d re ss [1 5 ..8 ] ALE E x te rn a l D a ta B u s (re a d ) E x te rn a l D a ta B u s (w rite ) RD WR In te rn a l W a it S ta te Figure 24. External Data SRAM Memory Cycles without Wait State The external data SRAM memory access cycle with the Wait State bit enabled (Wait State active) is shown in Figure 25. T1 T2 T3 T4 System Clock O External Address [7..0] External Address [15..8] ALE External Data Bus (read) External Data Bus (write) RD WR Figure 25. External Data SRAM Memory Cycles with Wait State 5-21 I/O Memory The I/O space definition of the AT90S8515 is shown in the following table: Table 1. AT90S8515 I/O Space Address Hex $3F ($5F) $3E ($5E) $3D ($5D) $3B ($5B) $3A ($A) $39 ($59) $38 ($58) $35 ($55) $33 ($53) $32 ($52) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $25 ($45) $24 ($44) $21 ($41) $1F ($3E) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) SPH SPL GIMSK GIFR TIMSK TIFR MCUCR TCCR0 TCNT0 TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L WDTCR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR USR UCR UBRR ACSR Name SREG Function Status REGister Stack Pointer High Stack Pointer Low General Interrupt MaSK register General Interrupt Flag Register Timer/Counter Interrupt MaSK register Timer/Counter Interrupt Flag register MCU general Control Register Timer/Counter0 Control Register Timer/Counter0 (8-bit) Timer/Counter1 Control Register A Timer/Counter1 Control Register B Timer/Counter1 High Byte Timer/Counter1 Low Byte Timer/Counter1 Output Compare Register A High Byte Timer/Counter1 Output Compare Register A Low Byte Timer/Counter1 Output Compare Register B High Byte Timer/Counter1 Output Compare Register B Low Byte T/C 1 Input Capture Register High Byte T/C 1 Input Capture Register Low Byte Watchdog Timer Control Register EEPROM Address Register High Byte EEPROM Address Register Low Byte EEPROM Data Register EEPROM Control Register Data Register, Port A Data Direction Register, Port A Input Pins, Port A Data Register, Port B Data Direction Register, Port B Input Pins, Port B Data Register, Port C Data Direction Register, Port C Input Pins, Port C Data Register, Port D Data Direction Register, Port D Input Pins, Port D SPI I/O Data Register SPI Status Register SPI Control Register UART I/O Data Register UART Status Register UART Control Register UART Baud Rate Register Analog Comparator Control and Status Register Note: reserved and unused locations are not shown in the table 5-22 AT90S8515 AT90S8515 All the different AT90S8515 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details. When using the I/O specific commands, IN, OUT,SBIS and SBIC, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the SRAM address in parentheses. The different I/O and peripherals control registers are explained in the following chapters. THE STATUS REGISTER - SREG The AVR status register - SREG - at I/O space location $3F ($5F) is defined as: Bit $3F ($5F) Read/Write Initial value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG Bit 7 - I : Global Interrupt Enable: The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the interrupt mask registers - GIMSK and TIMSK. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. Bit 6 - T : Bit Copy Storage: The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. Bit 5 - H : Half Carry Flag: The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. Bit 4 - S : Sign Bit, S = N V : The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the Instruction Set Description for detailed information. Bit 3 - V : Two's Complement Overflow Flag: The two's complement overflow flag V supports two's complement arithmetics. See the Instruction Set Description for detailed information. Bit 2 - N : Negative Flag: The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. Bit 1 - Z : Zero Flag: The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. Bit 0 - C : Carry Flag: The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 5-23 THE STACK POINTER - SP The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S8515 supports up to 64 kB external SRAM, all 16-bits are used. Bit $3E ($5E) $3D ($5D) 15 SP15 SP7 7 Read/Write R/W R/W Initial value 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when data is pushed onto the Stack with subroutine CALL and interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt IRET. Reset and Interrupt Handling The AT90S8515 provides 12 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0 etc. Table 2. Reset and Interrupt Vectors Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Program Address $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C Source RESET INT0 INT1 TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0, OVF SPI, STC UART, RX UART, UDRE UART, TX ANA_COMP Interrupt Definition Hardware Pin and Watchdog Reset External Interrupt Request 0 External Interrupt Request 1 Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Overflow Serial Transfer Complete UART, Rx Complete UART Data Register Empty UART, Tx Complete Analog Comparator 5-24 AT90S8515 AT90S8515 The most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c ; $00d ... MAIN: ... TIM1_COMPA ; Timer1 compareA Handle SPI_HANDLE ; SPI TX Handle UART_RXC UART_DRE UART_TXC ANA_COMP ; UART RX Complete Handle ; UDR Empty Handle ; UART TX Complete Handle ; Analog Comparator Handle RESET SOURCES The AT90S8515 has three sources of reset: * Power-On Reset. The MCU is reset when a supply voltage is applied to the VCC and GND pins. * External Reset. The MCU is reset when a low level is present on the RESET pin for more than two XTAL cycles * Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled. During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 26 shows the reset logic. Table 3 defines the timing and electrical parameters of the reset circuitry. Figure 26. Reset Logic 5-25 Table 3. Reset Characteristics (VCC = 5.0V) Symbol VPOT VRST tPOR tTOUT tTOUT Parameter Power-On Reset Threshold Voltage RESET Pin Threshold Voltage Power-On Reset Period Reset Delay Time-Out Period FSTRT Unprogrammed Reset Delay Time-Out Period FSTRT Programmed 2 11 1.0 Min 1.8 Typ 2 VCC/2 3 16 1.1 4 21 1.2 Max 2.2 Units V V ms ms ms POWER-ON RESET A Power-On Reset (POR) circuit ensures that the device is not started until VCC has reached a safe level. As shown in Figure 26, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after VCC has reached the Power-On Threshold voltage - VPOT, regardless of the VCC rise time (see Figure 27 and Figure 28). The total reset period is the Power-On Reset period - tPOR + the Delay Time-out period - tTOUT. The FSTRT fuse bit in the Flash can be programmed to give a shorter start-up time if a ceramic resonator or any other fast-start oscillator is used to clock the MCU. As the pin is pulled high by an on-chip resistor, the pin can be left unconnected if no external reset is required. Connecting to VCC will have the same effect. By holding the pin low for a period after VCC has been applied, the Power-On Reset period can be extended. Refer to Figure 29 for a timing example on this. Figure 27. MCU Start-Up, RESET Tied to VCC or Unconnected. Rapidly Rising VCC 5-26 AT90S8515 AT90S8515 Figure 28. MCU Start-Up, RESET Tied to VCC or Unconnected. Slowly Rising VCC Figure 29. MCU Start-Up, RESET Controlled Externally 5-27 EXTERNAL RESET An external reset is generated by a low level on the RESET pin. The RESET pin must be held low for at least two crystal clock cycles. When reaches the Reset Threshold Voltage - VRST on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired. Figure 30. External Reset During Operation WATCHDOG RESET When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT . Refer to Page 5-43 for details on operation of the Watchdog. Figure 31. Watchdog Reset During Operation INTERRUPT HANDLING The AT90S8515 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK Timer/Counter Interrupt Mask register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software must set (one) the I-bit to enable interrupts. When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. 5-28 AT90S8515 AT90S8515 THE GENERAL INTERRUPT MASK REGISTER - GIMSK Bit $3B ($5B) Read/Write Initial value 7 INT1 R/W 0 6 INT0 R/W 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 GIMSK Bit 7 - INT1 : External Interrupt Request 1 Enable: When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also "external Interrupts". Bit 6 - INT0 : External Interrupt Request 0 Enable: When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also "External Interrupts." Bits 5..0 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and always read as zero. THE GENERAL INTERRUPT FLAG REGISTER - GIFR Bit $3A ($5A) Read/Write Initial value 7 INTF1 R/W 0 6 INTF0 R/W 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 GIMSK Bit 7 - INTF1 : External Interrupt Flag1: When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Bit 6 - INTF0 : External Interrupt Flag0: When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Bits 5..0 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and always read as zero. THE TIMER/COUNTER INTERRUPT MASK REGISTER - TIMSK Bit $39 ($59) Read/Write Initial value 7 TOIE1 R/W 0 6 OCIE1A R/W 0 5 OCIE1B R/W 0 4 R 0 3 TICIE1 R/W 0 2 R 0 1 TOIE0 R/W 0 0 R 0 TIMSK Bit 7 - TOIE1 : Timer/Counter1 Overflow Interrupt Enable: When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer/Counter1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. When Timer/Counter1 is in PWM mode, the Timer Overflow flag is set when the counter changes counting direction at $0000. 5-29 Bit 6 - OCE1A :Timer/Counter1 Output CompareA Match Interrupt Enable: When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs. The CompareA Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. Bit 5 - OCIE1B :Timer/Counter1 Output CompareB Match Interrupt Enable: When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs. The CompareB Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. Bit 4 - Res : Reserved bit: This bit is a reserved bit in the AT90S8515 and always reads zero. Bit 3 - TICIE1 : Timer/Counter1 Input Capture Interrupt Enable: When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP. The Input Capture Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. Bit 2 - Res : Reserved bit: This bit is a reserved bit in the AT90S8515 and always reads zero. Bit 1 - TOIE0 : Timer/Counter0 Overflow Interrupt Enable: When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $008) is executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. Bit 0 - Res : Reserved bit: This bit is a reserved bit in the AT90S8515 and always reads zero. THE TIMER/COUNTER INTERRUPT FLAG REGISTER - TIFR Bit $38 ($58) Read/Write Initial value 7 TOV1 R/W 0 6 OCF1A R/W 0 5 OCIFB R/W 0 4 R 0 3 ICF1 R/W 0 2 R 0 1 TOV0 R/W 0 0 R 0 TIFR Bit 7 - TOV1 : Timer/Counter1 Overflow Flag: The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. Bit 6 - OCF1A : Output Compare Flag 1A: The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare match Interrupt is executed. Bit 5 - OCF1B : Output Compare Flag 1B: The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1 is cleared by writing a logic one to the flag.. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare match Interrupt is executed. Bit 4 - Res : Reserved bit: This bit is a reserved bit in the AT90S8515 and always reads zero. 5-30 AT90S8515 AT90S8515 Bit 3 - ICF1 : - Input Capture Flag 1: The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. Bit 2 - Res : Reserved bit: This bit is a reserved bit in the AT90S8515 and always reads zero. Bit 1 - TOV0 : Timer/Counter0 Overflow Flag: The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG Ibit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. Bit 0 - Res : Reserved bit: This bit is a reserved bit in the AT90S8515 and always reads zero. EXTERNAL INTERRUPTS The external interrupts are triggered by the INT1 and INT0 pins.Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. The external interrupts are set up as described in the specification for the MCU Control Register - MCUCR. INTERRUPT RESPONSE TIME The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. After the 4 clock cycles the program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the Stack, and the Stack Pointer is incremented by 2. When AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register - SREG - is not handled by the AVR hardware, neither for interrupts nor for subroutines. For the interrupt handling routines requiring a storage of the SREG, this must be performed by user software. For Interrupts triggered by events that can remain static (E.g. the Output Compare Register1 A matching the value of Timer/Counter1) the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event occurs the next time. MCU CONTROL REGISTER - MCUCR The MCU Control Register contains control bits for general MCU functions. Bit $35 ($55) Read/Write Initial value 7 SRE R/W 0 6 SRW R/W 0 5 SE R/W 0 4 SM R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR Bit 7 - SRE : External SRAM Enable: When the SRE bit is set (one), the external data SRAM is enabled, and the pin functions AD0-7 (Port A), A8-15 (Port C), WR and RD (Port D) are activated as the alternate pin functions. Then the SRE bit overrides any pin direction settings in the respective data direction registers. See "The SRAM Data Memory - Internal and External" for description of the External SRAM pin functions. When the SRE bit is cleared (zero), the external data SRAM is disabled, and the normal pin and data direction settings are used. 5-31 Bit 6 - SRW : External SRAM Wait State: When the SRW bit is set (one), a one cycle wait state is inserted in the external data SRAM access cycle. When the SRW bit is cleared (zero), the external data SRAM access is executed with the normal two cycle scheme. See Figure 24 External Data SRAM Memory Cycles without Wait State and Figure 25: External Data SRAM Memory Cycles with Wait State. Bit 5 - SE : Sleep Enable: The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. Bit 4 - SM : Sleep Mode: This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph "Sleep Modes" below. Bit 3, 2 - ISC11, ISC10 : Interrupt Sense Control 1 bit 1 and bit 0: The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK is set. The level and edges on the external INT1 pin that activate the interrupt are defined in the following table: Table 4. Interrupt 1 Sense Control ISC11 0 0 1 1 ISC10 0 1 0 1 Description The low level of INT1 generates an interrupt request. Reserved The falling edge of INT1 generates an interrupt request. The rising edge of INT1 generates an interrupt request. Note: When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Otherwise an interrupt can occur when the bits are changed. Bit 1, 0 - ISC01, ISC00 : Interrupt Sense Control 0 bit 1 and bit 0: The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set. The level and edges on the external INT0 pin that activate the interrupt are defined in the following table: Table 5. Interrupt 0 Sense Control ISC01 0 0 1 1 ISC00 0 1 0 1 Description The low level of INT0 generates an interrupt request. Reserved The falling edge of INT0 generates an interrupt request. The rising edge of INT0 generates an interrupt request. Note: When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Otherwise an interrupt can occur when the bits are changed. Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector. Note that if a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the oscillator start-up time of 16 ms. Otherwise, the interrupt flag may return to zero before the MCU starts executing. 5-32 AT90S8515 AT90S8515 IDLE MODE When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset. If wakeup from the Analog Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status register - ACSR. This will reduce power consumption during Idle Mode. POWER DOWN MODE When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the external oscillator is stopped. The user can select whether the watchdog shall be enabled during power-down mode. If the watchdog is enabled, it will wake up the MCU when the Watchdog Time-out period expires. If the watchdog is disabled, only an external reset or an external level triggered interrupt can wake up the MCU. Timer / Counters The AT90S8515 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting. The Timer/Counter Prescaler Figure 32 shows the general Timer/Counter prescaler. Figure 32. Timer/Counter Prescaler The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the two Timer/Counters, added selections as CK, external source and stop, can be selected as clock sources. 5-33 The 8-Bit Timer/Counter0 Figure 33 shows the block diagram for Timer/Counter0. The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Register - TCCR0. The overflow status flag is found in the Timer/Counter Insterrupt Flag Register - TIFR. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register - TIMSK. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. Figure 33. Timer/Counter0 Block Diagram THE TIMER/COUNTER0 CONTROL REGISTER - TCCR0 Bit $33 ($53) Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0 Bits 7,6 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and always read zero. Bits 2,1,0 - CS02, CS01, CS00 : Clock Select0, bit 2,1 and 0: The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0. 5-34 AT90S8515 AT90S8515 Table 6. Clock 0 Prescale Select CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter0 is stopped. CK CK / 8 CK / 64 CK / 256 CK / 1024 External Pin T0, falling edge External Pin T0, rising edge The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual data direction control register (cleared to zero gives an input pin). THE TIMER COUNTER 0 - TCNT0 Bit $32 ($52) Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 5-35 The 16-Bit Timer/Counter1 Figure 34 shows the block diagram for Timer/Counter1. Figure 34. Timer/Counter1 Block Diagram The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The different status flags (overflow, compare match and capture event) and control signals are found in the Timer/Counter1 Control Registers TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIMSK. When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions. The Timer/Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B - OCR1A and OCR1B as the data sources to be compared to the Timer/Counter1 contents. The Output Compare functions include optional clearing of the counter on compareA match, and actions on the Output Compare pins on both compare matches. Timer/Counter1 can also be used as a 8, 9 or 10-bit Pulse With Modulator. In this mode the counter and the OCR1A/ OCR1B registers serve as a dual glitch-free stand-alone PWM with centered pulses. Refer to Page 5-41 for a detailed description on this function. 5-36 AT90S8515 AT90S8515 The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture Register - ICR1, triggered by an external event on the Input Capture Pin - ICP. The actual capture event settings are defined by the Timer/Counter1 Control Register - TCCR1B. In addition, the Analog Comparator can be set to trigger the Input Capture. Refer to the section, "The Analog Comparator", for details on this. The ICP pin logic is shown in Figure 35. Figure 35. ICP Pin Schematic Diagram The Timer/Counter1 input capture noise canceler block diagram is shown in Figure 36. Figure 36. The Input Capture Noise Canceler If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples before the capture is activated. The input pin signal is sampled at XTAL clock frequency. THE TIMER/COUNTER1 CONTROL REGISTER A - TCCR1A Bit $2F ($4F) Read/Write Initial value 7 COM1A1 R/W 0 6 COM1A0 R/W 0 5 COM1B1 R/W 0 4 COM1B0 R/W 0 3 R 0 2 R 0 1 PWM11 R/W 0 0 PWM10 R/W 0 TCCR1A 5-37 Bits 7,6 - COM1A1, COM1A0 : Compare Output Mode1A, bits 1 and 0: The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 7. Bits 5,4 - COM1B1, COM1B0 : Compare Output Mode1B, bits 1 and 0: The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. The following control configuration is given: Table 7. Compare 1 Mode Select COM1X1 0 0 1 1 COM1X0 0 1 0 1 Description Timer/Counter1 disconnected from output pin OC1X Toggle the OC1X output line. Clear the OC1X output line (to zero). Set the OC1X output line (to one). X = A or B In PWM mode, these bits have a different function. Refer to Table 11 for a detailed description. When changing the COM1X1/COM1X0 bits, Output Compare Interrupts 1 must be disabled by clearing their Interrupt Enable bits in the TIMSK Register. Otherwise an interrupt can occur when the bits are changed. Bits 3..2 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and always read zero. Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select Bits: These bits select PWM operation of Timer/Counter1 as specified in Table 8. This mode is described on Page 5-41. Table 8. PWM Mode Select PWM11 0 0 1 1 PWM10 0 1 0 1 Description PWM operation of Timer/Counter1 is disabled Timer/Counter1 is an 8-bit PWM Timer/Counter1 is a 9-bit PWM Timer/Counter1 is a 10-bit PWM THE TIMER/COUNTER1 CONTROL REGISTER B - TCCR1B Bit $2E ($4E) Read/Write Initial value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 R 0 4 R 0 3 CTC1 R/w 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B Bit 7 - ICNC1 : Input Capture1 Noise Canceler (4 CKs): When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. 5-38 AT90S8515 AT90S8515 Bit 6 - ICES1 : Input Capture1 Edge Select: While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. Bits 5, 4 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and always read zero. Bit 3 - CTC1 : Clear Timer/Counter1 on Compare match: When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, the Timer/Counter1 continues counting until it is stopped, cleared, wraps around (overflow) or changes direction. In PWM mode, this bit has no effect. Bits 2,1,0 - CS12, CS11, CS10 : Clock Select1, bit 2,1 and 0: The Clock Select1 bits 2,1 and 0 define the prescaling source of Timer/Counter1. Table 9. Clock 1 Prescale Select CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter1 is stopped. CK CK / 8 CK / 64 CK / 256 CK / 1024 External Pin T1, falling edge External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual direction control register (cleared to zero gives an input pin). THE TIMER/COUNTER1 - TCNT1H AND TCNT1L Bit $2D ($4D) $2C ($4C) 7 Read/Write R/W R/W Initial value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 15 MSB LSB 0 R/W R/W 0 0 14 13 12 11 10 9 8 TCNT1H TCNT1L This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). * TCNT1 Timer/Counter1 Write: When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16-bit register write operation. 5-39 * TCNT1 Timer/Counter1 Read: When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1AH AND OCR1AL Bit $2B ($4B) $2A ($4A) 7 Read/Write R/W R/W Initial value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 15 MSB LSB 0 R/W R/W 0 0 14 13 12 11 10 9 8 OCR1AH OCR1AL TIMER/COUNTER1 OUTPUT COMPARE REGISTER - OCR1BH AND OCR1BL Bit $29 ($49) $28 ($48) 7 Read/Write R/W R/W Initial value 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 15 MSB LSB 0 R/W R/W 0 0 14 13 12 11 10 9 8 OCR1BH OCR1BL The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. THE TIMER/COUNTER1 INPUT CAPTURE REGISTER - ICR1H AND ICR1L Bit $25 ($45) $24 ($44) 7 Read/Write R R Initial value 0 0 6 R R 0 0 5 R R 0 0 4 R R 0 0 3 R R 0 0 2 R R 0 0 1 R R 0 0 15 MSB LSB 0 R R 0 0 14 13 12 11 10 9 8 ICR1H ICR1L The input capture register is a 16-bit read-only register. 5-40 AT90S8515 AT90S8515 When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. TIMER/COUNTER1 IN PWM MODE When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A - OCR1A and the Output Compare Register1B - OCR1B, form a dual 8, 9 or 10-bit, free-running, glitch-free and phase correct PWM with outputs on the PD5(OC1A) and OC1B pins. Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 10) , when it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the 10 least significant bits of OCR1A or OCR1B, the PD5(OC1A)/OC1B pins are set or cleared according to the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A. Refer to Table 11 for details. Table 10. Timer TOP Values and PWM Frequency PWM Resolution 8-bit 9-bit 10-bit Timer TOP value $00FF (255) $01FF (511) $03FF(1023) Frequency fTC1/510 fTC1/1022 fTC1/2046 Table 11. Compare1 Mode Select in PWM Mode COM1X1 0 0 1 1 COM1X0 0 1 0 1 Effect on OCX1 Not connected Not connected Cleared on compare match, upcounting. Set on compare match, downcounting (non-inverted PWM). Cleared on compare match, downcounting. Set on compare match, upcounting (inverted PWM). Note: X = A or B 5-41 Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 37 for an example. Figure 37. Effects on Unsynchronized OCR1 Latching When OCR1 contains $0000 or TOP, the output OC1A/OC1B is held low or high according to the settings of COM1A1/ COM1A0 or COM1B1/COM1B0. This is shown in Table 12: Table 12. PWM Outputs OCR1X = $0000 or TOP COM1X1 1 1 1 1 COM1X0 0 0 1 1 OCR1X $0000 TOP $0000 TOP Output OC1X L H H L Note: X = A or B In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter changes direction at $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are enabled. This does also apply to the Timer Output Compare1 flags and interrupts. 5-42 AT90S8515 AT90S8515 The Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1MHz This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted from 16 to 2048 ms. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S8515 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to Page 5-28. To prevent unintentional disabling of the watchdog, a special turn-off secuence must be followed when the watchdog is disabled.Refer to the description of the Watchdog Timer Control Regiter for details Figure 38. Watchdog Timer THE WATCHDOG TIMER CONTROL REGISTER - WDTCR Bit $21 ($41) Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 WDTTOE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR Bits 7..5 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and will always read as zero. Bit 4 - WDTOE : Watch Dog Turn-Off Enable: This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure. Bit 3 - WDE : Watch Dog Enable: When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logcal one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog. 5-43 Bits 2..0 - WDP2, WDP1, WDP0 : Watch Dog Timer Prescaler 2, 1 and 0: The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 13. Table 13. Watch Dog Timer Prescale Select (Typical Values at VCC = 5V) WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 Timeout Period 16 ms 32 ms 64 ms 128 ms 256 ms 512 ms 1024 ms 2048 ms EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. An EEPROM brown-out detection prevents writing to the EEPROM if VCC is below a certain level. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed. THE EEPROM ADDRESS REGISTER - EEARH AND EEARL Bit $1F ($3F) $1E ($3E) 15 EEAR7 7 Read/Write R/W R/W Initial value 8 8 14 EEAR6 6 R/W R/W 0 0 13 EEAR5 5 R/W R/W 0 0 12 EEAR4 4 R/W R/W 0 0 11 EEAR3 3 R/W R/W 0 0 10 EEAR2 2 R/W R/W 0 0 9 EEAR1 1 R/W R/W 0 0 8 EEAR9 EEAR0 0 R/W R/W 0 0 EEARH EEARL The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 512. THE EEPROM DATA REGISTER - EEDR Bit $1D ($3D) Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR Bits 7..0 - EEDR7..0 : EEPROM Data: For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 5-44 AT90S8515 AT90S8515 THE EEPROM CONTROL REGISTER - EECR Bit $1C ($3C) Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 EEMWE R/W 0 1 EEWE R/W 0 0 EERE R/W 0 EECR Bit 7..3 - Res : Reserved bits: These bits are reserved bits in the AT90S2313 and will always read as zero. Bit 2 - EEMWE : EEPROM Master Write Enable: The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. Bit 1 - EEWE : EEPROM Write Enable: The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional) 3. Write new EEPROM data to EEDR (optional) 4. Write a logical one to the EEMWE bit in EECR 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. Bit 0 - EERE : EEPROM Read Enable: The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for two cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined. 5-45 The Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8515 and peripheral devices or between several AT90S8515 devices. The AT90S8515 SPI features include the following: * * * * * * * * Full-Duplex, 3-Wire Synchronous Data Transfer Master or Slave Operation 5 Mbit/s Bit Frequency (max.) LSB First or MSB First Data Transfer Four Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wakeup from Idle Mode (Slave Mode Only) Figure 39. SPI Block Diagram 5-46 AT90S8515 AT90S8515 The interconnection between master and slave CPUs with SPI is shown in Figure 40. The PB7(SCK) pin is the clock output in the master mode and is the clock input in the slave mode. Writing to the SPI data register of the master CPU starts the SPI clock generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR register becomesset, an interrupt is requested. The Slave Select input, PB4(SS), is set low to select an individual SPI device as a slave. The two shift registers in the Master and the Slave can be considered as one distributed 16-bit circular shift register. This is shown in Figure 40. When data is shifted from the master to the slave, data is also shifted in the opposite direction, simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged. Figure 40. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that characters to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first character is lost. When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is overriden according to the following table: Table 14.SPI Pin Overrides Pin MOSI MISO SCK SS Direction, Master SPI User Defined Input User Defined User Defined Direction, Slave SPI Input User Defined Input Input SS Pin Functionality When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. If SS is configured as an input, it must be hold high to ensure Master SPI operatin. If, in master mode, the SS pin is input, and is driven low by peripheral circuitry, the SPI system interpretes this as that another master selects the SPI as a slave and will start sending data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, the interrupt routine will be executed. 5-47 Thus, when interrupt-driven SPI transmittal is used in master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. Once the MSTR bit has been cleared by a slave select, it must be set by the user. When the SPI is configured as a slave, the SS is always input. When SS is held low, the SPI is activated and MISO becomes an output if configured so by the user. All other pins are inputs When SS is driven low, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 41 and Figure 42. Figure 41. SPI Transfer Format with CPHA = 0 Figure 42. SPI Transfer Format with CPHA = 1 5-48 AT90S8515 AT90S8515 THE SPI CONTROL REGISTER - SPCR Bit $0D ($2D) Read/Write Initial value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 1 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR Bit 7 - SPIE : SPI Interrupt Enable: This bit causes setting of the SPIF bit in the SPSR register to execute the SPI interrupt provided that global interrupts are enabled. Bit 6 - SPE : SPI Enable: When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. Bit 5 - DORD : Data ORDer: When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. Bit 4 - MSTR : Master/Slave Select: This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low whil MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. Bit 3 - CPOL : Clock POLarity: When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 41 and Figure 42 for additional information. Bit 2 - CPHA : Clock PHAse: Refer to Figure 41 or Figure 42 for the functionality of this bit. Bits 1,0 - SPR1, SPR0 : SPI Clock Rate Select 1 and 0: These two bits control the SCK rate of the device configured as a master. SPR1 and SPR2 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency fcl is shown in the following table: Table 15. Relationship Between SCK and the Oscillator Frequency SPR1 0 0 1 1 SPR0 0 1 0 1 SCK Frequency fcl / 4 fcl / 16 fcl / 64 fcl / 128 THE SPI STATUS REGISTER - SPSR Bit $0E ($2E) Read/Write Initial value 7 SPIF R 0 6 WCOL R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 SPSR Bit 7 - SPIF : SPI Interrupt Flag: When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF 5-49 flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI Data Register (SPDR). Bit 6 - WCOL : Write COLlision flag: The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. During data transfer, the result of reading the SPDR register may be incorrect, and writing to it will have no effect. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register. Bit 5..0 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and will always read as zero. The SPI interface on the AT90S8515 is also used for program memory and EEPROM downloading or uploading. See Page 5-78 for serial programming and verification. THE SPI DATA REGISTER - SPDR Bit $0F ($2F) Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 SPDR The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. The UART The AT90S8515 features a full duplex Universal Asynchronous Receiver and Transmitter (UART). The main features are: * * * * * * * * Baud rate generator generates any baud rate High baud rates at low XTAL frequencies 8 or 9 bits data Noise filtering Overrun detection Framing Error detection False Start Bit detection Three separate interrupts on TX Complete, TX Data Register Empty and RX Complete 5-50 AT90S8515 AT90S8515 Data Transmission A block schematic of the UART transmitter is shown in Figure 43. Figure 43. UART Transmitter Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred from UDR to the Transmit shift register when: * A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately. * A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. If the 10(11)-bit Transmitter shift register is empty or when, data is transferred from UDR to the shift register. At this time the UDRE (UART Data Register Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9 bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit shift register. 5-51 On the Baud Rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When no new data has been written, and the stop bit has been present on TXD for one bit length, the TX Complete Flag, TXC, in USR is set. The TXEN bit in UCR enables the UART transmitter when set (one). By clearing this bit (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to the PD1 pin regardless of the setting of the DDD1 bit in DDRB. Data Reception Figure 44 shows a block diagram of the UART Receiver Figure 44. UART Receiver The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1 to 0-transition, the receiver samples the RXD pin at samples 8, 9 and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise spike and the receiver starts looking for the next 1 to 0-transition. 5-52 AT90S8515 AT90S8515 If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in Figure 45. Figure 45. Sampling Received Data When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical zeros, the Framing Error (FE) flag in the UART Status Register (USR) is set. Before reading the UDR register, the user should always check the FE bit to detect Framing Errors. Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one for received data. When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is accessed. If 9 bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit shift register when data is transferred to UDR. If, after having received a character, the UDR register has not been read since the last receive, the OverRun (OR) flag in UCR is set. This means that the last data byte shifted into to the shift register could not be transferred to UDR and has been lost. The OR bit is buffered, and is updated when the valid data byte in UDR is read. Thus, the user should always check the OR bit after reading the UDR register in order to detect any overruns. By clearing the RXEN bit in the UCR register, the receiver is disabled. This means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART Receiver will be connected to the PD0 pin regardless of the setting of the DDD0 bit in DDRB. UART Control THE UART I/O DATA REGISTER - UDR Bit $0C ($2C) Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 UDR The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read. THE UART STATUS REGISTER - USR Bit $0B ($2B) Read/Write Initial value 7 RXC R 0 6 TXC R 0 5 UDRE R 1 4 FE R 0 3 OR R 0 2 R 0 1 R 0 0 R 0 USR The USR register is a read-only register providing information on the UART Status. Bit 7 - RXC: UART Receive Complete: This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. 5-53 Bit 6 - TXC : UART Transmit Complete: This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit. Bit 5 - UDRE : UART Data Register Empty: This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. Bit 4 - FE : Framing Error: This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. Bit 3 - OR : OverRun: This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. Bits 2..0 - Res : Reserved bits: These bits are reserved bits in the AT90S8515 and will always read as zero. THE UART CONTROL REGISTER - UCR Bit $0A ($2A) Read/Write Initial value 7 RXCIE R/W 0 6 TXCIE R/W 0 5 UDRIE R/W 0 4 RXEN R/W 0 3 TXEN R/W 0 2 CHR9 R/W 0 1 RXB8 R 0 0 TXB8 W 0 UCR Bit 7 - RXCIE : RX Complete Interrupt Enable: When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed provided that global interrupts are enabled. Bit 6 - TXCIE : TX Complete Interrupt Enable: When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed provided that global interrupts are enabled. Bit 5 - UDRIE : UART Data Register Empty Interrupt Enable: When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled. Bit 4 - RXEN : Receiver Enable: This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared. 5-54 AT90S8515 AT90S8515 Bit 3 - TXEN : Transmitter Enable: This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted. Bit 2 - CHR9 : 9 Bit Characters: When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity bit. Bit 1 - RXB8 : Receive Data Bit 8 When CHR9 is set (one), RXB8 is the 9th data bit of the received character. Bit 0 - TXB8 : Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted. THE BAUD RATE GENERATOR The baud rate generator is a frequency divider which generates baud-rates according to the following equation: fCK BAUD = ------------------------------------16 ( UBRR + 1 ) * BAUD = Baud-Rate * fck= Crystal Clock frequency * UBRR= Contents of the UART Baud Rate register, UBRR (0-255) For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR settings in Table 16. UBRR values which yield an actual baud rate differing less than 2% from the target baud rate, are bolded in the table. 5-55 Table 16. UBRR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 1.8432 MHz %Error 2 MHz %Error 2.4576 MHz %Error 2400 UBRR= 25 0.2 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 63 0.0 UBRR= UBRR= UBRR= UBRR= 4800 12 0.2 23 0.0 25 0.2 31 0.0 6 7.5 UBRR= 9600 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 15 0.0 3 7.8 UBRR= 8 3.7 UBRR= 10 3.1 14400 UBRR= 7 0.0 UBRR= 2 7.8 UBRR= 6 7.5 UBRR= 19200 UBRR= 5 0.0 UBRR= 7 0.0 1 7.8 UBRR= 3 7.8 UBRR= 4 6.3 28800 UBRR= 3 0.0 UBRR= 0 7.8 UBRR= 1 7.8 UBRR= 2 12.5 57600 UBRR= 1 0.0 UBRR= 0 84.3 UBRR= 0 7.8 UBRR= 0 25.0 115200 UBRR= 0 0.0 UBRR= Baud Rate 3.2768 MHz %Error 3.6864 MHz %Error 4 MHz %Error 4.608 MHz %Error 2400 UBRR= 84 0.4 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 4800 UBRR= 42 0.8 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 9600 UBRR= 20 1.6 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0 16 2.1 UBRR= 14400 UBRR= 13 1.6 UBRR= 15 0.0 UBRR= 19 0.0 UBRR= 10 3.1 UBRR= UBRR= UBRR= 19200 11 0.0 12 0.2 14 0.0 8 3.7 UBRR= 28800 UBRR= 6 1.6 UBRR= 7 0.0 UBRR= 9 0.0 3 12.5 UBRR= 3 7.8 UBRR= 57600 UBRR= 3 0.0 UBRR= 4 0.0 1 12.5 UBRR= 1 7.8 UBRR= 2 20.0 115200 UBRR= 1 0.0 UBRR= Baud Rate 7.3728 MHz %Error 8 MHz %Error 9.216 MHz %Error 11.059 MHz %Error UBRR= 191 UBRR= 207 UBRR= 239 2400 0.0 0.2 0.0 UBRR= 287 4800 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 UBRR= 143 0.0 9600 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 UBRR= 71 0.0 14400 UBRR= 31 0.0 UBRR= 34 0.8 UBRR= 39 0.0 UBRR= 47 0.0 19200 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0 UBRR= 35 0.0 16 2.1 UBRR= 28800 UBRR= 15 0.0 UBRR= 19 0.0 UBRR= 23 0.0 8 3.7 UBRR= 57600 UBRR= 7 0.0 UBRR= 9 0.0 UBRR= 11 0.0 3 7.8 UBRR= 115200 UBRR= 3 0.0 UBRR= 4 0.0 UBRR= 5 0.0 Baud Rate 14.746 MHz %Error 16 MHz %Error 18.432 MHz %Error 20 MHz %Error UBRR= 416 UBRR= 479 UBRR= 520 2400 UBRR= 383 4800 UBRR= 191 0.0 UBRR= 207 0.2 UBRR= 239 0.0 UBRR= 259 9600 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 UBRR= 129 0.2 UBRR= UBRR= UBRR= UBRR= 14400 63 0.0 68 0.6 79 0.0 86 0.2 19200 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 UBRR= 64 0.2 28800 UBRR= 31 0.0 UBRR= 34 0.8 UBRR= 39 0.0 UBRR= 42 0.9 16 2.1 UBRR= 57600 UBRR= 15 0.0 UBRR= 19 0.0 UBRR= 21 1.4 THE UART BAUD RATE REGISTER - UBRR Bit $09 ($29) Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 UBRR The UBRR register is an 8-bit read/write register which specifies the UART Baud Rate according to the equation on the previous page. 5-56 AT90S8515 AT90S8515 The Analog Comparator The analog comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When the voltage on the positive pin PB2 (AIN0) is higher than the voltage on the negative pin PB3 (AIN1), the Analog Comparator Output, ACO is set (one). The comparator's output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 46. Figure 46. Analog Comparator Block Diagram THE ANALOG COMPARATOR CONTROL AND STATUS REGISTER - ACSR Bit $08 ($28) Read/Write Initial value 7 ACD R/W 0 6 R 0 5 ACO R 0 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR Bit 7 - ACD : Analog Comparator Disable When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. It is most commonly used if power consumption during Idle Mode is critical, and wake-up from the analog comparator is not required. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. Bit 6 - Res : Reserved bit: This bit is a reserved bit in the AT90S8515 and will always read as zero. Bit 5 - ACO : Analog Comparator Output: ACO is directly connected to the comparator output. Bit 4 - ACI : Analog Comparator Interrupt Flag: This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Bit 3 - ACIE : Analog Comparator Interrupt Enable: When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When cleared (zero), the interrupt is disabled. 5-57 Bit 2 - ACIC : Analog Comparator Input Capture enable: When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the analog comparator and the Input Capture function is given. To make the comparator trigger the Timer/ Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one). Bits 1,0 - ACIS1, ACIS0 : Analog Comparator Interrupt Mode Select: These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 17. Table 17. ACIS1/ACIS0 Settings ACIS1 0 0 1 1 ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle Reserved Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge Note: When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed. I/O-Ports Port A PORT A is an 8-bit bi-directional I/O port. Three data memory address locations are allocated for the Port A, one each for the Data Register - PORTA, $1B($3B), Data Direction Register - DDRA, $1A($3A) and the Port A Input Pins - PINA, $19($39). The Port A Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pullups. The PORT A output buffers can sink 20mA and thus drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current (IIL) if the internal pullups are activated. The PORT A pins have alternate functions related to the optional external data SRAM. PORT A can be configured to be the multiplexed low-order address/data bus during accesses to the external data memory. In this mode, PORT A has internal pullups. When PORT A is set to the alternate function by the SRE - External SRAM Enable - bit in the MCUCR - MCU Control Register, the alternate settings override the data direction register. 5-58 AT90S8515 AT90S8515 THE PORT A DATA REGISTER - PORTA Bit $1B ($3B) Read/Write Initial value 7 PORTA7 R/W 0 6 PORTA6 R/W 0 5 PORTA5 R/W 0 4 PORTA4 R/W 0 3 PORTA3 R/W 0 2 PORTA2 R/W 0 1 PORTA1 R/W 0 0 PORTA0 R/W 0 PORTA THE PORT A DATA DIRECTION REGISTER - DDRA Bit $1A ($3A) Read/Write Initial value 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA THE PORT A INPUT PINS ADDRESS - PINA Bit $19 ($39) Read/Write Initial value 7 PINA7 R Hi-Z 6 PINA6 R Hi-Z 5 PINA5 R Hi-Z 4 PINA4 R Hi-Z 3 PINA3 R Hi-Z 2 PINA2 R Hi-Z 1 PINA1 R Hi-Z 0 PINA0 R Hi-Z PINA The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the PORTA Data Latch is read, and when reading PINA, the logical values present on the pins are read. PORTA AS GENERAL DIGITAL I/O All 8 bits in PORT A are equal when used as digital I/O pins. PAn, General I/O pin: The DDAn bit in the DDRA register selects the direction of this pin, if DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTAn has to be cleared (zero) or the pin has to be configured as an output pin. Table 18. DDAn Effects on PORT A Pins DDAn 0 0 1 1 PORTAn 0 1 0 1 I/O Input Input Output Output Pull up No Yes No No Comment Tri-state (Hi-Z) PAn will source current (IIL) if ext. pulled low. Push-Pull Zero Output Push-Pull One Output n: 7,6...0, pin number. 5-59 PORT A SCHEMATICS Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure. Figure 47. PORTA Schematic Diagrams (Pins PA0 - PA7) Port B Port B is an 8-bit bi-directional I/O port. Three data memory address locations are allocated for the Port B, one each for the Data Register - PORTB, $18($38), Data Direction Register - DDRB, $17($37) and the Port B Input Pins - PINB, $16($36). The Port B Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pullups. The Port B output buffers can sink 20mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current (IIL) if the internal pullups are activated. 5-60 AT90S8515 AT90S8515 The Port B pins with alternate functions are shown in the following table: Table 19. Port B Pins Alternate Functions Port Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Alternate Functions T0 (Timer/Counter 0 external counter input) T1 (Timer/Counter 1 external counter input) AIN0 (Analog comparator positive input) AIN1 (Analog comparator negative input) SS (SPI Slave Select input) MOSI (SPI Bus Master Output/Slave Input) MISO (SPI Bus Master Input/Slave Output) SCK (SPI Bus Serial Clock) When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate function description. THE PORT B DATA REGISTER - PORTB Bit $18 ($38) Read/Write Initial value 7 PORTB7 R/W 0 6 PORTB6 R/W 0 5 PORTB5 R/W 0 4 PORTB4 R/W 0 3 PORTB3 R/W 0 2 PORTB2 R/W 0 1 PORTB1 R/W 0 0 PORTB0 R/W 0 PORTB THE PORT B DATA DIRECTION REGISTER - DDRB Bit $17 ($37) Read/Write Initial value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB THE PORT B INPUT PINS ADDRESS - PINB Bit $16 ($36) Read/Write Initial value 7 PINB7 R Hi-Z 6 PINB6 R Hi-Z 5 PINB5 R Hi-Z 4 PINB4 R Hi-Z 3 PINB3 R Hi-Z 2 PINB2 R Hi-Z 1 PINB1 R Hi-Z 0 PINB0 R Hi-Z PINB The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the PORTB Data Latch is read, and when reading PINB, the logical values present on the pins are read. PORTB AS GENERAL DIGITAL I/O All 8 bits in port B are equal when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. 5-61 Table 20. DDBn Effects on Port B Pins DDBn 0 0 1 1 PORTBn 0 1 0 1 I/O Input Input Output Output Pull up No Yes No No Comment Tri-state (Hi-Z) PBn will source current (IIL) if ext. pulled low. Push-Pull Zero Output Push-Pull One Output n: 7,6...0, pin number. ALTERNATE FUNCTIONS OF PORTB The alternate pin configuration is as follows: SCK - PORTB, Bit 7: SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further detatils. MISO - PORTB, Bit 6: MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further detatils. MOSI - PORTB, Bit 5: MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further detatils. SS - PORTB, Bit 4: SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further detatils. AIN1 - PORTB, Bit 3 AIN1, Analog Comparator Negative Input. When configured as an input (DDB3 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB3 is cleared (zero)), this pin also serves as the negative input of the on-chip analog comparator. AIN0 - PORTB, Bit 2 AIN0, Analog Comparator Positive Input. When configured as an input (DDB2 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB2 is cleared (zero)), this pin also serves as the positive input of the on-chip analog comparator. T1 - PORTB, Bit 1: T1, Timer/Counter1 counter source. See the timer description for further details T0 - PORTB, Bit 0: T0: Timer/Counter0 counter source. See the timer description for further details. 5-62 AT90S8515 AT90S8515 PORT B SCHEMATICS Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 48. PORTB Schematic Diagram (Pins PB0 and PB1) Figure 49. PORTB Schematic Diagram (Pins PB2 and PB3) 5-63 Figure 50. PORTB Schematic Diagram (Pin PB4) Figure 51. PORTB Schematic Diagram (Pin PB5) 5-64 AT90S8515 AT90S8515 Figure 52. PORTB Schematic Diagram (Pin PB6) Figure 53. PORTB Schematic Diagram (Pin PB7) 5-65 Port C PORT C is an 8-bit bi-directional I/O port. Three data memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data Direction Register - DDRC, $14($34) and the Port C Input Pins - PINC, $13($33). The Port C Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pullups. The PORT C output buffers can sink 20mA and thus drive LED displays directly. When pins PC0 to PC7 are used as inputs and are externally pulled low, they will source current (IIL) if the internal pullups are activated. The PORT C pins have alternate functions related to the optional external data SRAM. PORT C can be configured to be the high-order address byte during accesses to external data memory. In this mode, PORT C uses internal pullups when emitting 1's. When PORT C is set to the alternate function by the SRE - External SRAM Enable - bit in the MCUCR - MCU Control Register, the alternate settings override the data direction register. THE PORT C DATA REGISTER - PORTC Bit $15 ($35) Read/Write Initial value 7 PORTC7 R/W 0 6 PORTC6 R/W 0 5 PORTC5 R/W 0 4 PORTC4 R/W 0 3 PORTC3 R/W 0 2 PORTC2 R/W 0 1 PORTC1 R/W 0 0 PORTC0 R/W 0 PORTC THE PORT C DATA DIRECTION REGISTER - DDRC Bit $14 ($34) Read/Write Initial value 7 DDC7 R/W 0 6 DDC6 R/W 0 5 DDC5 R/W 0 4 DDC4 R/W 0 3 DDC3 R/W 0 2 DDC2 R/W 0 1 DDC1 R/W 0 0 DDC0 R/W 0 DDRC THE PORT C INPUT PINS ADDRESS - PINC Bit $13 ($33) Read/Write Initial value 7 PINC7 R Hi-Z 6 PINC6 R Hi-Z 5 PINC5 R Hi-Z 4 PINC4 R Hi-Z 3 PINC3 R Hi-Z 2 PINC2 R Hi-Z 1 PINC1 R Hi-Z 0 PINC0 R Hi-Z PINC The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the PORTC Data Latch is read, and when reading PINC, the logical values present on the pins are read. PORTC AS GENERAL DIGITAL I/O All 8 bits in PORT C are equal when used as digital I/O pins. PCn, General I/O pin: The DDCn bit in the DDRC register selects the direction of this pin, if DDCn is set (one), PCn is configured as an output pin. If DDCn is cleared (zero), PCn is configured as an input pin. If PORTCn is set (one) when the pin configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTCn has to be cleared (zero) or the pin has to be configured as an output pin. Table 21. DDCn Effects on PORT C Pins DDCn 0 0 1 1 PORTCn 0 1 0 1 I/O Input Input Output Output Pull up No Yes No No Comment Tri-state (Hi-Z) PCn will source current (IIL) if ext. pulled low. Push-Pull Zero Output Push-Pull One Output n: 7...0, pin number 5-66 AT90S8515 AT90S8515 PORT C SCHEMATICS Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure. Figure 54. PORTC Schematic Diagram (Pins PC0 - PC7) Port D Port D is an 8 bit bi-directional I/O port with internal pullups. Three data memory address locations are allocated for the Port D, one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31) and the Port D Input Pins - PIND, $10($30). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current (IIL) if the pullups are activated. Some Port D pins have alternate functions as shown in the following table: Table 22. Port D Pins Alternate Functions Port Pin PD0 PD1 PD2 PD3 PD5 PD6 PD7 Alternate Function RDX (UART Input line ) TDX (UART Output line) INT0 (External interrupt 0 input) INT1 (External interrupt 1 input) OC1A (Timer/Counter1 Output compareA match output) WR (Write strobe to external memory) RD (Read strobe to external memory) When the pins are used for the alternate function the DDRD and PORTD register has to be set according to the alternate function description. 5-67 THE PORT D DATA REGISTER - PORTD Bit $12 ($32) Read/Write Initial value 7 PORTD7 R/W 0 6 PORTD6 R/W 0 5 PORTD5 R/W 0 4 PORTD4 R/W 0 3 PORTD3 R/W 0 2 PORTD2 R/W 0 1 PORTD1 R/W 0 0 PORTD0 R/W 0 PORTD THE PORT D DATA DIRECTION REGISTER - DDRD Bit $11 ($31) Read/Write Initial value 7 DDD7 R/W 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD THE PORT D INPUT PINS ADDRESS - PIND Bit $10 ($30) Read/Write Initial value 7 PIND7 R Hi-Z 6 PIND6 R Hi-Z 5 PIND5 R Hi-Z 4 PIND4 R Hi-Z 3 PIND3 R Hi-Z 2 PIND2 R Hi-Z 1 PIND1 R Hi-Z 0 PIND0 R Hi-Z PIND The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the PORTD Data Latch is read, and when reading PIND, the logical values present on the pins are read. PORTD AS GENERAL DIGITAL I/O PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull up resistor is activated. To switch the pull up resistor off the PDn has to be cleared (zero) or the pin has to be configured as an output pin. Table 23. DDDn Bits on Port D Pins DDDn 0 0 1 1 PORTDn 0 1 0 1 I/O Input Input Output Output Pull up No Yes No No Comment Tri-state (Hi-Z) PDn will source current (IIL) if ext. pulled low. Push-Pull Zero Output Push-Pull One Output n: 7,6...0, pin number. ALTERNATE FUNCTIONS OF PORTD RD - PORTD, Bit 7: RD is the external data memory read control strobe. WR - PORTD, Bit 6: WR is the external data memory write control strobe. OC1- PORTD, Bit 5: OC1, Output compare match output: The PD5 pin can serve as an external output when the Timer/Counter1 compare matches. The PD5 pin has to be configured as an output (DDD5 set (one)) to serve this function. See the Timer/Counter1 description for further details, and how to enable the output. The OC1 pin is also the output pin for the PWM mode timer function. 5-68 AT90S8515 AT90S8515 INT1 - PORTD, Bit 3: INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details, and how to enable the source. INT0 - PORTD, Bit 2: INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details, and how to enable the source. TXD - PORTD, Bit 1: Transmit Data (Data output pin for the UART). When the UART transmitter is enabled, this pin is configured as an output regardless of the value of DDRD1. RXD - PORTD, Bit 0: Receive Data (Data input pin for the UART). When the UART receiver is enabled this pin is configured as an output regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical one in PORTD0 vill turn on the internal pull-up. PORTD SCHEMATICS Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 55. PORTD Schematic Diagram (Pin PD0) 5-69 Figure 56. PORTD Schematic Diagram (Pin PD1) Figure 57. PORTD Schematic Diagram (Pins PD2 and PD3) 5-70 AT90S8515 AT90S8515 Figure 58. PORTD Schematic Diagram (Pin PD4) Figure 59. PORTD Schematic Diagram (Pin PD5) 5-71 Figure 60. PORTD Schematic Diagram (Pin PD6) Figure 61. PORTD Schematic Diagram (Pin PD7) 5-72 AT90S8515 AT90S8515 Memory Programming Program Memory Lock Bits The AT90S8515 MCU provides two lock bits which can be left unprogrammed (`1') or can be programmed (`0') to obtain the additional features listed in Table 24. Table 24. Lock Bit Protection Modes Program Lock Bits Mode 1 2 3 LB1 1 0 0 LB2 1 1 0 No program lock features Further programming of the Flash is disabled Same as mode 2, but verify is also disabled. Protection Type Note: The Lock Bits can only be erased with the Chip Erase operation. Fuse Bits The AT90S8515 has two fuse bits, SPIEN and FSTRT. * When SPIEN is programmed (`0'), Serial Program Downloading is enabled. Default value is programmed (`0'). * When FSTRT is programmed (`0'), the short start-up time is selected. Default value is unprogrammed (`1'). Parts with this bit pre-programmed (`0') can be delivered on demand. These bits are not accessible in Serial Programming Mode and are not affected by a chip erase. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space, and for the AT90S8515 they are: 1. 2. 3. $000: $1E (indicates manufactured by Atmel) $001: $93 (indicates 8kB Flash memory) $002: $01 (indicates 90S8515 device when $001 is $93) Programming the Flash and EEPROM Atmel's AT90S8515 offers 8K bytes of in-system reprogrammable Flash Program memory and 512 bytes of EEPROM Data memory. The AT90S8515 is normally shipped with the on-chip Flash Program and EEPROM Data memory arrays in the erased state (i.e. contents = $FF) and ready to be programmed. This device supports a High-Voltage (12V) Parallel programming mode and a Low-Voltage Serial programming mode. The +12V is used for programming enable only, and no current of significance is drawn by this pin. The serial programming mode provides a convenient way to download the Program and Data into the AT90S8515 inside the user's system. The Program and Data memory arrays on the AT90S8515 are programmed byte-by-byte in either programming modes. For the EEPROM, an auto-erase cycle is provided with the self-timed programming operation in the serial programming mode. 5-73 Parallel Programming This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory + Program Memory Lock bits and Fuse bits in the AT90S8515. Figure 62. Parallel Programming SIGNAL NAMES In this section, some pins of the AT908515 are referenced by signal names describing their functionality during parallel programming rather than their pin names. Pins not described in the following table are referenced by pin names. Table 25. Pin Name Mapping Signal Name in Programming Mode RDY / BSY OE WR BS XA0 XA1 Pin Name PD1 PD2 PD3 PD4 PD5 PD6 I/O O I I I I I Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (Active Low) Write Pulse (Active Low) Byte Select XTAL Action Bit 0 XTAL Action Bit 1 The XA1/XA0 bits determine the action taken when the XTAL1 pin is given a positive pulse. The bit settings are shown in the following table: Table 26. XA1 and XA0 Coding XA1 0 0 1 1 XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or Low address byte for Flash determined by BS) Load Data (High or Low data byte for Flash determined by BS) Load Command No Action, Idle 5-74 AT90S8515 AT90S8515 When pulsing WR or OE, the command loaded determines the action on input or output. The command is a byte where the different bits are assigned functions as shown in the following table: Table 27. Command Byte Bit Coding Bit# 7 6 5 4 3 2 1 0 Meaning when Set Chip Erase Write Fuse Bits. Located in the data byte at the following bit positions: D5: SPIEN Fuse, D0: FSTRT Fuse (Note: Write `0' to program, `1' to erase) Write Lock Bits. Located in the data byte at the following bit positions: D1: LB1, D0: LB2 (Note: write `0' to program) Write Flash or EEPROM (determined by bit 0) Read signature row Read Lock and Fuse Bits. Located in the data byte at the following bits positions: D7: LB1, D6: LB2, D5: SPIEN Fuse, D0: FSTRT Fuse (Note: `0' means programmed) Read from Flash or EEPROM (determined by bit 0) 0 : Flash Access, 1 : EEPROM Access ENTER PROGRAMMING MODE The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5 V between VCC and GND. 2. Set RESET and BS pins to `0' and wait at least 100 ns. 3. Apply 12V to and wait at least 100 ns before changing BS. CHIP ERASE The chip erase will erase the Flash and EEPROM memories plus Lock bits. The lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A chip erase must be performed before the chip is programmed. Load Command "Chip Erase" 1. Set XA1, XA0 to `10'. This enables command loading. 2. Set BS to `0'. 3. Set PB(7:0) to `1000 0000'. This is the command for Chip erase. 4. Give XTAL1 a positive pulse. This loads the command, and starts the erase of the Flash and EEPROM arrays. After pulsing XTAL1, give WR a negative pulse to enable lock bit erase at the end of the erase cycle, then wait for at least 10 ms. Chip erase does not generate any activity on the RDY/BSY pin. PROGRAMMING THE FLASH Load Command "Program Flash" 1. Set XA1, XA0 to `10'. This enables command loading. 2. Set BS to `0' 3. Set PB(7:0) to `0001 0000'. This is the command for Flash programming. 4. Give XTAL1 a positive pulse. This loads the command. Load Address Low byte 1. Set XA1, XA0 to `00'. This enables address loading. 2. Set BS to `0'. This selects Low address. 3. Set PB(7:0) = Address Low byte ($00 - $FF) 4. Give XTAL1 a positive pulse. This loads the Address Low byte. 5-75 Load Address High byte 1. Set XA1, XA0 to `00'. This enables address loading. 2. Set BS to `1'. This selects High address. 3. Set PB(7:0) = Address High byte ($00 - $0F) 4. Give XTAL1 a positive pulse. This loads the Address High byte. Load Data byte 1. Set XA1, XA0 to `01'. This enables data loading. 2. Set PB(7:0) = Data Low byte ($00 - $FF) 3. Give XTAL1 a positive pulse. This loads the Data byte. Write Data Low byte 1. Set BS to (`0'). 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. Load Data byte 1. Set XA1, XA0 to `01'. This enables data loading. 2. Set PB(7:0) = Data High byte ($00 - $FF) 3. Give XTAL1 a positive pulse. This loads the Data byte. Write Data High byte 1. Set BS to `1'. 2. Give WR a negative pulse. This starts programming of the data byte. RDY / BSY goes low. 3. Wait until RDY / BSY goes high to program the next byte. The loaded command and address are retained in the device during programming. To simplify programming, the following should be considered. * The command for Flash programming needs only be loaded before programming of the first byte. * Address High byte needs only be loaded before programming a new 256 word page in the Flash. Figure 63. Programming Flash Low Byte 5-76 AT90S8515 AT90S8515 Figure 64. Programming Flash High Byte PROGRAMMING THE EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0001 0001'. 2. Load Low EEPROM Address ($00 - $FF) 3. Load High EEPROM Address ($00 - $01) 4. Load Low EEPROM Data ($00 - $FF) 5. Give WR a negative pulse and wait for RDY/BSY to go high. The Command needs only be loaded before programming the first byte. READING THE FLASH The algorithm for reading the Flash memory is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 0010'. 2. Load Low Address ($00 - $FF) 3. Load High Address ($00 - $0F) 4. Set OE to `0', and BS to `0'. The Low Data byte can now be read at PB(7:0) 5. Set BS to `1'. The High Data byte can now be read from PB(7:0) 6. Set OE to `1'. The Command needs only be loaded before reading the first byte. READING THE EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 0011'. 2. Load Low EEPROM Address ($00 - $FF) 3. Load High EEPROM Address ($00 - $FF) 4. Set OE to `0', and BS to `0'. The EEPROM Data byte can now be read at PB(7:0) 5. Set OE to `1'. The Command needs only be loaded before reading the first byte. 5-77 PROGRAMMING THE FUSE BITS The algorithm for programming the Fuse bits is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0100 0000'. 2. Load Data. Bit 5 = `0' programs the SPIEN Fuse bit. Bit 5 = `1' erases the SPIEN Fuse bit. Bit 0 = `0' programs the FSTRT fuse bit. Bit 5 = `1' erases the FSTRT fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. PROGRAMMING THE LOCK BITS The algorithm for programming the Lock bits is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0010 0000'. 2. Load Data. Bit 2 = '0' programs Lock Bit2 Bit 1 = '0' programs Lock Bit1 3. Give WR a negative pulse and wait for RDY/BSY to go high. The lock bits can only be cleared by executing a chip erase. READING THE FUSE AND LOCK BITS The algorithm for reading the Fuse and Lock bits is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 0100'. 2. Set OE to `0', and BS to `1'. The Status of Fuse and Lock bits can now be read at PB(7:0) Bit 7: Lock Bit1 (`0' means programmed) Bit 6: Lock Bit2 (`0' means programmed) Bit 5: SPIEN Fuse (`0' means programmed, `1' means erased) Bit 0: FSTRT Fuse (`0' means programmed, `1' means erased) 3. Set OE to `1'. Observe especially that BS needs to be set to `1'. READING THE SIGNATURE BYTES The algorithm for reading the Signature Bytes bits is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 1000'. 2. Load Low address ($00 - $02) 3. Set OE to `0', and BS to `0'. The Selected Signature byte can now be read at PB(7:0) 4. Set OE to `1'. The command needs only be programmed before reading the first byte. Serial Downloading Both the Program and Data memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into $FF. The Program and EEPROM memory arrays have separate address spaces: $0000 to $0FFF for Program memory and $0000 to $001FF for EEPROM memory. 5-78 AT90S8515 AT90S8515 Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2.The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 1 XTAL1 clock cycle High: > 4 XTAL1 clock cycles SERIAL PROGRAMMING ALGORITHM To program and verify the AT90S8515 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 28): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to `0'. (If the programmer can not guarantee that SCK is held low during power-up, RESET must be given a positive pulse after SCK has been set to `0'.) If a crystal is not connected across pins XTAL1 and XTAL2, apply a 0 to 20 MHz clock to the XTAL1 pin. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI/PB5. Refer to the above section for minimum high and low periods for the serial clock input (SCK). 3. If a chip erase is performed (must be done to erase the Flash), wait 10ms, give RESET a positive pulse and start over again from Step 2. 4. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. The next byte can be written after 4 ms. 5. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/PB6. 6. At the end of the programming session, RESET can be set high to commence normal operation. 7. Power-off sequence (if needed): Set XTAL1 to `0' (if a crystal is not used). Set RESET to `1'. Turn VCC power off 5-79 Table 28. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Programming Enable Chip Erase 1010 1100 Operation Byte 2 0101 0011 Byte 3 xxxx xxxx Byte4 xxxx xxxx Enable Serial Programming after RESET goes low. Chip erase both 8K & 512byte memory arrays Read H(high or low) data o from Program memory at word address a:b Write H(high or low) data i to Program memory at word address a:b Read data o from EEPROM memory at address a:b Write data i to EEPROM memory at address a:b Write lock bits. Set bits 1,2='0' to program lock bits. Read Device Code o at address b 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Read Program Memory 0010 H000 xxxx aaaa bbbb bbbb oooo oooo Write Program Memory 0100 H000 xxxx aaaa bbbb bbbb iiii iiii Read EEPROM Memory Write EEPROM Memory Write Lock Bits Read Device Code 1010 0000 xxxx xxx0 bbbb bbbb oooo oooo 1100 0000 xxxx xxx0 bbbb bbbb iiii iiii 1010 1100 0011 0000 111x x21x xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx oooo oooo Notes: a = address high bits b = address low bits H = 0 - Low byte, 1 - High Byte o = data out i = data in x = don't care 1 = lock bit 1 2 = lock bit 2 Programming Characteristics Figure 65. Serial Downloading Waveforms 5-80 AT90S8515 AT90S8515 Figure 66. Serial Programming and Verify When writing serial data to the AT90S8515, data is clocked on the rising edge of CLK. When reading data from the AT90S8515, data is clocked on the falling edge of CLK. See Figure 65 for an explanation. Absolute Maximum Ratings* Operating Temperature ................................. -40C to +105C Storage Temperature..................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground.......................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V I/O Pin Maximum Current ........................................... 40.0 mA Maximum Current VCC and GND............................. 140.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5-81 DC Characteristics TA = -40C to 85C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol VIL VIH VIH1 VOL VOH IOH IOL RRST RI/O Parameter Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage (Ports B,C,D) Output High Voltage (Ports B,C,D) Output Source Current (Ports B,C,D) Output Sink Current (Port B,C,D) Reset Pulldown Resistor I/O Pin Pull-Up Resistor Active Mode, 3V, 4MHz ICC Power Supply Current Idle Mode 3V, 4MHz (1) Condition Min -0.5 Typ Max 0.2 Vcc - 0.1 VCC + 0.5 VCC + 0.5 0.5 Units V V V V V (Except XTAL1, RESET) (XTAL1, RESET) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 2.7V IHI = 10 mA, VCC = 5V IHI = 5 mA, VCC = 2.7V VCC = 5V VCC = 2.7V VCC = 5V VCC = 2.7V 0.2 VCC + 0.9 0.7 VCC 4.5 10 5 20 10 10 35 3.5 1000 50 <1 20 1 5 750 500 10 50 120 mA mA k k mA A A A mV nA ns WDT enabled, 3V ICC VACIO IACLK tACPD Power Down Mode(2) WDT disabled, 3V Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V VCC = 5V Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum total IOL for all output pins: 80 mA Port A: 26 mA Ports A, B, D: 15 mA Maximum total IOL for all output pins: 70 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V. 5-82 AT90S8515 AT90S8515 External Clock Drive Waveforms External Clock Drive Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time VCC = 2.7V to 6.0V Min 0 100 40 40 10 10 Max 10 VCC = 4.0V to 6.0V Min 0 41.7 16.7 16.7 4.15 4.15 Max 20 Units MHz ns ns ns ns ns 5-83 Ordering Information Ordering Code AT90S8515-JC AT90S8515-PC AT90S8515-JI AT90S8515-PI Package 44J 40P6 44J 40P6 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Package Type 44J 40P6 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40 Lead, 0.600" Wide, Plastic Dual in Line Package (PDIP) 5-84 AT90S8515 AT90S8515 AT90S8515 Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) ... $00 ($20) Name SREG SPH SPL Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR Reserved TCCR0 TCNT0 Reserved Reserved TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL Reserved Reserved ICR1H ICR1L Reserved Reserved WDTCR Reserved Reserved EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR USR UCR UBRR ACSR Reserved Reserved Bit 7 I SP15 SP7 INT1 INTF1 TOIE1 TOV1 Bit 6 T SP14 SP6 INT0 INTF0 OCIE1A OCF1A Bit 5 H SP13 SP5 OCIE1B OCF1B Bit 4 S SP12 SP4 - Bit 3 V SP11 SP3 TICIE1 ICF1 Bit 2 N SP10 SP2 - Bit 1 Z SP9 SP1 TOIE0 TOV0 Bit 0 C SP8 SP0 - Page 5-23 5-24 5-24 5-29 5-29 5-29 5-30 SRE SRW SE - SM - ISC11 - ISC10 CS02 ISC01 CS01 ISC00 CS00 5-31 5-34 5-35 Timer/Counter0 (8 Bit) COM1A1 COM1A0 COM1B1 COM1B0 ICNC1 ICES1 Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte CTC1 CS12 PWM11 CS11 PWM10 CS10 5-37 5-38 5-39 5-39 5-40 5-40 5-40 5-40 Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte 5-40 5-40 - - - WDTOE WDE WDP2 WDP1 WDP0 5-43 EEPROM Address Register EEPROM Data Register PORTA7 PORTA6 DDA7 DDA6 PINA7 PINA6 PORTB7 PORTB6 DDB7 DDB6 PINB7 PINB6 PORTC7 PORTC6 DDC7 DDC6 PINC7 PINC6 PORTD7 PORTD6 DDD7 DDD6 PIND7 PIND6 SPI Data Register SPIF WCOL SPIE SPE UART I/O Data Register RXC TXC RXCIE TXCIE UART Baud Rate Register ACD - PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 DORD UDRE UDRIE ACO PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 MSTR FE RXEN ACI PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 CPOL OR TXEN ACIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 CPHA CHR9 ACIC EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 SPR1 RXB8 ACIS1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPR0 TXB8 ACIS0 5-44 5-44 5-45 5-59 5-59 5-59 5-61 5-61 5-61 5-66 5-66 5-66 5-68 5-68 5-68 5-50 5-49 5-49 5-53 5-53 5-54 5-56 5-57 5-85 AT90S8515 Instruction Set Summary Mnemonics Operands Description Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One's Complement NEG Rd Two's Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled 5-86 AT90S8515 AT90S8515 Mnemonics Operands Description Move Between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset Operation Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer) Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None #Clocks 1 1 2 2 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR 5-87 |
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